The present disclosure relates to an image sensor, a driving method, and an electronic apparatus, and more particularly, to an image sensor, a driving method, and an electronic apparatus that are capable of achieving speedup of an image sensor, for example.
There is a demand for an image sensor that has an increased number of pixels and achieves speedup, but increasing the number of pixels and achieving speedup are in a trade-off relationship.
In other words, in order to achieve the speedup of the image sensor, for example, it is necessary to short a settling time of a voltage of a VSL (Vertical Signal Line) (hereinafter, also referred to as VSL voltage), the voltage varying according to a signal read out from a pixel.
On the other hand, in the case of increasing the number of pixels of the image sensor, a parasitic capacitance of a VSL for transferring signals read out from pixels arranged in a column direction increases. This increase of the parasitic capacitance hinders the shortening of the settling time of the VSL voltage.
In order to shorten the settling time of the VSL voltage, it is effective to increase a current provided by a current source, together with which an amplifier transistor that forms a pixel forms a source follower.
However, since the VSL has the parasitic capacitance, the current provided by the current source, which forms the source follower, decreases by an amount of a current flowing in the VSL from the parasitic capacitance. As a result, the shortening of the settling time of the VSL voltage is hindered.
In this regard, the applicant of the subject application has previously proposed a technique to shorten the settling time of the VSL voltage, that is, to achieve the speedup of the image sensor (solid-state imaging device) by adding a circuit (load element unit) that increases a current flowing in the VSL by an amount of a current flowing in the VSL from the parasitic capacitance (see Japanese Patent Application Laid-open No. 2011-234243).